DEGRADATION OF SHORT-CHANNEL MOS TRANSISTORS STRESSED AT LOW TEMPERATURE

Modeling of random channel parameter variations in MOS transistors

Widely used approaches to modeling random effects and extracting random parameters in matching-critical circuits are based upon models derived under the widely accepted premise that distributed parameter devices can be modeled with lumped parameter models. In this paper, a new stochastic approach based upon a distributed parameter model is presented that offers improvement in predicting the eff...

Implications of Negative Bias Temperature Instability in Power MOS Transistors

As the device dimensions in metal-oxide-silicon (MOS) technologies have been continuously scaled down, a phenomenon called negative bias temperature instability (NBTI), which refers to the generation of positive oxide charge and interface traps in MOS structures under negative gate bias at elevated temperature, has been gaining in importance as one of the most critical mechanisms of MOS field e...

Floating-gate Mos Synapse Transistors

Measurement and Modeling of Short-Channel MOS Transistor Gate Capacitances

A flexible electrometer method for measuring the gate capacitances of smafl-geometry MOS transistors is described. This technique applies to standard test transistors without requiring any on-chip circuitry. Subfemtofarad accuracy and high resolution (better than 0.1 fF) have been achieved. This technique permits flexibility with regard to choices of dc biases and test devices and provides a go...

Short-Channel Poly-Si Thin-Film Transistors with Ultrathin Channel